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copyright ? cirrus logic, inc. 2007 (all rights reserved) http://www.cirrus.com 114 db, 192 khz, 6-ch annel a/d converter features ? advanced multi-bit delta-sigma architecture ? 24-bit conversion ? 114 db dynamic range ? -105 db thd+n ? supports audio sample rates up to 216 khz ? selectable audio interface formats ? left-justified, i2s, tdm ? 6-channel tdm interface formats ? low latency digital filter ? less than 535 mw power consumption ? on-chip oscillator driver ? operation as system clock master or slave ? auto-detect speed in slave mode ? differential analog architecture ? separate 1.8 v to 5 v logic supplies for control and serial ports ? high-pass filter for dc offset calibration ? overflow detection ? footprint compatible with the 8-channel cs5368 additional control port features ? supports standard i2c ? or spi? control interface ? individual channel hpf disable ? overflow detection for individual channels ? mute control for individual channels ? independent power-down control per channel pair digital audio voltage reference level translator level translator internal oscillator vd 3.3 - 5v control interface i2c, spi or pins configuration registers va 5v vlc 1.8 - 5v vls 1.8 - 5v 6 differential analog inputs device control decimation filter high pass filter multi-bit ? adc serial audio out pcm or tdm cs5366 july '07 ds626f2
2 ds626f2 cs5366 description the cs5366 is a complete 6-channel analog-to-digital conver ter for digital audio systems. it performs sampling, an- alog-to-digital conversion, and anti-alias filtering, generating 24-bit values for all 6-chann el inputs in serial form at sample rates up to 216 khz per channel. the cs5366 uses a 5th-order, multi-bit delta sigma modula tor followed by low latency di gital filtering and decima- tion, which removes the need for an external anti-aliasing f ilter. the adc uses a differenti al input architecture which provides excellent noise rejection. dedicated level translators for the serial port and contro l port allow seamless interf acing between the cs5366 and other devices operating over a wide rang e of logic levels. in addition, an on-c hip oscillator driver provides clocking flexibility and simplifies design. the cs5366 is the industry?s first audio a/d to support a high-speed tdm interface which provides a serial output of 6 channels of audio data with sample rates up to 216 khz within a single data stream . it further reduces layout complexity and relieves input/output cons traints in digital signal processors. the cs5366 is available in 48-pin lqfp package in both commercial (-40 to 85c) and automotive grades (-40 to +105c). the cdb5366 customer demonstration board is also available for device evaluation and implementation suggestions. please see ?ordering information? on page 41 for complete orde ring information. the cs5366 is ideal for high-end and pro-audio systems r equiring unrivaled sound quality, transparent conversion, wide dynamic range and negligible distortion, such as a/v receivers, digital mixing consoles, multi-channel record- ers, outboard converters, digital effect processors, and automotive audio systems.
ds626f2 3 cs5366 table of contents 1. pin description ............................................................................................................ ..................... 6 2. typical connection diagram ................................................................................................. .... 9 3. characteristics and specificatio ns .......... ................. ................ ................ ................ ......... 10 recommended operating conditions ................................................................................. 10 absolute ratings .......... ................ ................ ................ ............. ............. ............. ............. ......... 10 system clocking ......... ................ ................ ................ ................ ............. ............. ............ .......... 10 dc power ...................................................................................................................... .................. 11 logic levels ............. ................. ................ ................ ............. ............. ............. ............ ................ 11 psrr, vq and filt+ characteristics .................................................................................... 11 analog characteristics (commercial) .............................................................................. 12 analog performance (automotive) .................. ................................................................... 13 digital filter characteristics ............................................................................................. 14 overflow timeout .............................................................................................................. ........ 14 serial audio interface - i2s/lj timing ................................................................................... 15 serial audio interface - tdm timing ..................................................................................... 16 switching specifications - control port - i2c timing ................................................... 17 switching specifications - control port - spi timing .................................................. 18 4. applications ............................................................................................................... .................... 19 4.1 power ..................................................................................................................... ........................ 19 4.2 control port mode and stand-alone operation .............................................................................. 1 9 4.2.1 stand-alone mode ........................................................................................................ ......... 19 4.2.2 control port mode ....................................................................................................... .......... 19 4.3 master clock source ....................................................................................................... ............... 20 4.3.1 on-chip crystal oscillator driver ....................................................................................... ... 20 4.3.2 externally generated master clock ....................................................................................... 20 4.4 master and slave operation ................................................................................................ ........... 21 4.4.1 synchronization of multiple devices ..................................................................................... .21 4.5 serial audio interface (sai) format ......... .............................................................................. ......... 22 4.5.1 i2s and lj format ....................................................................................................... ........... 22 4.5.2 tdm format .............................................................................................................. ............ 23 4.5.3 configuring serial audio interface format ............................................................................ 23 4.6 speed modes ............................................................................................................... .................. 23 4.6.1 sample rate ranges ...................................................................................................... ...... 23 4.6.2 using m1 and m0 to set sa mpling parameters .................................................................... 23 4.6.3 master mode clock dividers .............................................................................................. ... 24 4.6.4 slave mode audio clocking with auto-detect ...................................................................... 24 4.7 master and slave clock frequencies ........................................................................................ ..... 25 4.8 reset ..................................................................................................................... ......................... 27 4.8.1 power-down mode ......................................................................................................... ....... 27 4.9 overflow detection ........................................................................................................ ................. 27 4.9.1 overflow in stand-alone mode ............................................................................................ .. 27 4.9.2 overflow in control port mode ........................................................................................... ... 27 4.10 analog connections ....................................................................................................... .............. 28 4.11 optimizing performance in tdm mode ....................................................................................... .29 4.12 dc offset control ........................................................................................................ ................. 29 4.13 control port operation ........................... ........................................................................ ............... 30 4.13.1 spi mode ............................................................................................................... .............. 30 4.13.2 i2c mode ............................................................................................................... ............... 31 5. register map ............................................................................................................... .................... 32 5.1 register quick reference ................................................................................................. ............ 32 5.2 00h (revi) chip id code & revision register ............................................................................... 32
4 ds626f2 cs5366 5.3 01h (gctl) global mode control register .................................................................................. .32 5.4 02h (ovfl) overflow status register ...................................................................................... ..... 33 5.5 03h (ovfm) overflow mask register ......... ............................................................................... .... 33 5.6 04h (hpf) high-pass filter register ...................................................................................... ....... 34 5.7 05h reserved ............................................................................................................. ................... 34 5.8 06h (pdn) power down register ............................................................................................ ...... 34 5.9 07h reserved ............................................................................................................. ................... 34 5.10 08h (mute) mute control register .............. ........................................................................... ..... 34 5.11 09h reserved ............................................................................................................ .................. 35 5.12 0ah (sden) sdout enable control register ............................................................................ 35 6. filter plots ............................................................................................................... ...................... 36 7. parameter definitions ...................................................................................................... .......... 39 8. package dimensions ........................................................................................................ ........... 40 thermal characteristics ...................................................................................................... .40 9. ordering information ....................................................................................................... ......... 41 10. revision history ......................................................................................................... ................ 41 list of figures figure 1. cs5366 pinout ....................................................................................................... ...................... 6 figure 2. typical connection diagram ............ .............................................................................. .............. 9 figure 3. i2s/lj timing ....................................................................................................... ....................... 15 figure 4. tdm timing .......................................................................................................... ..................... 16 figure 5. i2c timing .......................................................................................................... ........................ 17 figure 6. spi timing .......................................................................................................... ....................... 18 figure 7. crystal oscillator topology ......................................................................................... ............... 20 figure 8. master/slave clock flow ................. ............................................................................ .............. 21 figure 9. master and slave clocking for a multi-c hannel application ...................................................... 21 figure 10. i2s format ......................................................................................................... ....................... 22 figure 11. lj format .......................................................................................................... ....................... 22 figure 12. tdm format ......................................................................................................... .................... 23 figure 13. master mode clock div iders ......................................................................................... ........... 24 figure 14. slave mode auto-detect speed ............ ........................................................................... ........ 24 figure 15. recommended analog input buffer .................................................................................... ..... 28 figure 16. spi format ......................................................................................................... ...................... 30 figure 17. i2c write format ................................................................................................... ................... 31 figure 18. i2c read format .. .................................................................................................. .................. 31 figure 19. ssm passband ....................................................................................................... ................. 36 figure 20. dsm passband ....................................................................................................... ................. 36 figure 21. qsm passband ....................................................................................................... ................. 36 figure 22. ssm stopband ....................................................................................................... .................. 37 figure 23. dsm stopband ....................................................................................................... .................. 37 figure 24. qsm stopband ....................................................................................................... ................. 37 figure 25. ssm -1 db cutoff ........................ ........................................................................... .................. 38 figure 26. dsm -1 db cutoff .................................................................................................. .................. 38 figure 27. qsm -1 db cutoff ................................................................................................... .................. 38
ds626f2 5 cs5366 list of tables table 1. power supply pin definitions ......................................................................................... ............. 19 table 2. dif1 and dif0 pin settings ........................................................................................... ............. 23 table 3. m1 and m0 settings ................................................................................................... ................. 23 table 4. frequencies for 48 khz sample rate using lj/i2s ..................................................................... 25 table 5. frequencies for 96 khz sample rate using lj/i2s ..................................................................... 25 table 6. frequencies for 192 khz sample rate using lj/i2s ................................................................... 25 table 7. frequencies for 48 khz sample rate using tdm ....................................................................... 25 table 8. frequencies for 48 khz sample rate using tdm ....................................................................... 25 table 9. frequencies for 96 khz sample rate using tdm ....................................................................... 26 table 10. frequencies for 96 khz sample rate using tdm ..................................................................... 26 table 11. frequencies for 192 khz sample rate usi ng tdm ................................................................... 26 table 12. frequencies for 192 khz sample rate usi ng tdm ................................................................... 26
6 ds626f2 cs5366 1. pin description figure 1. cs5366 pinout dif1/ad1/cdin ref_gnd ain3+ sdout1/tdm vls tsto sdout3/tdm gnd sdout2 m0/sda/cdout ain5- ain1+ ain5+ ain6- ain6+ ain3- gnd gnd gnd gnd vd xti gnd vlc dif0/ad0/cs ain1- m1/scl/cclk lrck/fs sclk mclk xto ovfl clkmode mdiv rst 6 2 4 8 10 1 3 5 7 9 11 12 13 14 15 16 17 18 19 20 21 22 23 24 31 35 33 29 27 36 34 32 30 28 26 25 48 47 46 45 44 43 42 41 40 39 38 37 cs5366 filt+ ain2- va gnd gnd ain2+ gnd va ain4+ ain4- vq vx gnd
ds626f2 7 cs5366 pin name pin # pin description ain2+, ain2- ain4+, ain4- ain3+, ain3- ain6+, ain6- ain5+, ain5- ain1+, ain1- 1,2 11,12 13,14 43,44 45,46 47,48 differential analog ( inputs ) - audio signals are presented differently to the delta sigma modula- tors via the ain+/- pins. gnd 3,8 10,15 16,17 18,19 29,32 ground ( input ) - ground reference. must be connected to analog ground. va 4,9 analog power ( input ) - positive power supply for the analog section ref_gnd 5 reference ground ( input ) - for the internal sampling circuits. must be connected to analog ground. filt+ 6 positive voltage reference ( output ) - reference voltage for internal sampling circuits. vq 7 quiescent voltage ( output ) - filter connection for the inte rnal quiescent reference voltage. vx 20 crystal oscillator power ( input ) - also powers control logic to enable or disable oscillator cir- cuits. xti xto 21 22 crystal oscillator connections ( input/output ) - i/o pins for an external crystal which may be used to generate mclk. mclk 23 system master clock ( input/output ) - when a crystal is used, this pin acts as a buffered mclk source (output). when the oscillator function is not used, this pin acts as an input for the system master clock. in this case, the xti and xto pins must be tied low. lrck/fs 24 serial audio channel clock ( input/output ) in i2s mode serial audio channel select. when low, the odd channels are selected. in lj mode serial audio channel select. when high, the odd channels are selected. in tdm mode a frame sync signal. when high, it marks the beginning of a new frame of serial audio samples. in slave mode, this pin acts as an input pin. sclk 25 main timing clock for the serial audio interface ( input/output ) - during master mode, this pin acts as an output, and during slave mode it acts as an input pin. tsto 26 test out ( output ) - must be left unconnected. sdout2 27 serial audio data ( output ) - channels 3,4. vls 28 serial audio interface power - positive power for the serial audio interface. sdout1/tdm 30 serial audio data ( output ) - channels 1,2. tdm. sdout3/tdm 31 serial audio data ( output ) - channels 5,6. tdm is complementary tdm data. vd 33 digital power ( input ) - positive power supply for the digital section. vlc 35 control port interface power - positive power for th e control port interface. ovfl 36 overflow ( output, open drain ) - detects an overflow condition on both left and right channels. rst 41 reset ( input ) - the device enters a low power mode when low. stand-alone mode clkmode 34 clkmode (input) - setting this pin high places a divide-by-1.5 circuit in the mclk path to the core device circuitry. dif1 dif0 37 38 dif1, dif0 ( input ) - sets the serial audio interface format. m1 m0 39 40 mode selection ( input ) - determines the operational mode of the device. mdiv 42 mclk divider ( input ) - setting this pin high places a divide-by-2 circuit in the mclk path to the core device circuitry.
8 ds626f2 cs5366 control port mode clkmode 34 clkmode (input) - this pin is ignored in control port mode and the same functionality is obtained from the corresponding bit in the global control register. note: should be connected to gnd when using the part in control port mode. ad1/cdin 37 i2c format, ad1 ( input ) - forms the device address input ad[1]. spi format, cdin ( input ) - becomes the input data pin. ad0/cs 38 i2c format, ad0 ( input ) - forms the device address input ad[0]. spi format, cs (input) - acts as the active low chip select input. scl/cclk 39 i2c format, scl ( output ) - acts as the serial clock output from the cs5366. spi format, cclk ( output ) - acts as the serial clock output from the cs5366. sda/cdout 40 i2c format sda ( input/output ) - acts as an input/output data pin. spi format cdout ( output ) - acts as an output only data pin. mdiv 42 mclk divider ( input ) - this pin is ignored in control port mode and the same functionality is obtained from the corresponding bit in the global control register. note: should be connected to gnd when using the part in control port mode.
ds626f2 9 cs5366 2. typical conn ection diagram figure 2. typical connection diagram for analog buffer configurations, refer to cirrus applicati on note an241. also, a low-cost single-ended-to-differen- tial solution is provided on the customer evaluation board. filt+ d + va v +5v 5.1 1 f + sdout2 dif0/ad0/cs power down and mode settings 0.01 f mode0/sda/cdout mode1/scl/cclk ref_gnd vlc f ain + 1 ain - 1 channel 1 analog input buffer ain + 2 ain - 2 channel 2 analog input buffer ain + 3 ain - 3 channel 3 analog input buffer ain + 4 ain - 4 channel 4 analog input buffer ain + 5 ain - 5 channel 5 analog input buffer ain + 6 ain - 6 channel 6 analog input buffer 0.1 f vq gnd 220 f 0.1 f + 1 f gnd dif1/ad1/cdin rst ovfl 0.01 0.01 f +5v to 3.3v 1 f + a/d converter cs5366 sdout1/tdm sdout3/tdm sclk mclk timing logic and clock audio data processor mdiv clkmode reserved 4,9 39 36 37 38 41 42 34 30 27 31 26 24 25 23 lrck/fs +5v to 1.8v 33 6 5 7 8 47 48 1 2 13 14 11 12 45 46 43 44 3, 8, 10, 15, 16, 17, 18, 19, 29, 32 35 40 vls f 0.01 +5v to 1.8v 28 xti xto 21 22 +5v vx 20 resistor may only be used if vd is derived from va. if used, do not drive any other logic from vd.
10 ds626f2 cs5366 3. characteristics and specifications recommended operating conditions gnd = 0 v, all voltages with respect to 0 v. 1. tdm quad-speed mode specified to operate correctly at vls 3.14 v. absolute ratings operation beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. transient currents up to 100 ma on the analog input pins will not cause scr latch-up. system clocking parameter symbol min typ max unit dc power supplies: positive analog positive crystal positive digital positive serial logic positive control logic va vx vd vls vlc 4.75 4.75 3.14 1.71 1 1.71 5.0 5.0 3.3 3.3 3.3 5.25 v ambient operating temperature (-cqz) (-dqz) t ac t aa -40 -40 - - 85 105 c parameter symbol min typ max units dc power supplies: positive analog positive crystal positive digital positive serial logic positive control logic va vx vd vls vlc -0.3 - +6.0 v input current i in -10 - + 10 ma analog input voltage v in -0.3 va+0.3 v digital input voltage v ind vl+0.3 ambient operating temperature (power applied) t a -50 +95 c storage temperature t stg -65 +150 parameter symbol min typ max unit input master clock frequency mclk 0.512 55.05 mhz input master clock duty cycle t clkhl 40 60 %
ds626f2 11 cs5366 dc power mclk = 12.288 mhz; master mode. gnd = 0 v. 1. power-down is defined as rst = low with all clocks and data lines held static at a valid logic level. logic levels psrr, vq and filt + characteristics mclk = 12.288 mhz; master mode. valid with the recommended capacitor values on filt+ and vq as shown in the ?typical connection diagram?. parameter symbol min typ max unit power supply current va = 5 v (normal operation) vx = 5 v vd = 5 v vd = 3.3 v vls, vlc = 5 v vls, vlc = 3.3 v i a i x i d i d i l i l - - - - - - 76 4 60 37 6 3 84 8 66 40 8 5 ma ma ma ma ma ma power supply current va = 5 v (power-down) (note 1) vls, vlc,vd = 5 v i a i d - - 50 500 - - a a power consumption (normal operation) all supplies = 5 v va = 5 v, vd = vls = vlc = 3.3 v (power-down) (note 1) - - - - - - 730 532 2.75 830 609 - mw mw mw mw parameter symbol min typ max units high-level input voltage %vls/vlc v ih 70 - - % low-level input voltage %vls/vlc v il 30 high-level output voltage at 100 a load %vls/vlc v oh 85 - low-level output voltage at -100 a load %vls/vlc v ol -15 ovfl current sink -4 ma input leakage current logic pins only i in -10 - 10 a parameter symbol min typ max unit power supply rejection ratio at (1 khz) psrr - 65 - db v q nominal voltage output impedance maximum allowable dc current source/sink - va/2 25 10 - v k a filt+ nominal voltage output impedance maximum allowable dc current source/sink - va 4.4 10 - v k a
12 ds626f2 cs5366 analog characterist ics (commercial) test conditions (unless other wise specified). va = 5 v, vd = vls = vlc 3.3 v, and t a = 25 c. full-scale input sine wave. measurement bandwidth is 10 hz to 20 khz. parameter symbol min typ max unit single-speed mode fs = 48 khz dynamic range a-weighted unweighted 108 105 114 111 - - db total harmonic distortion + noise -1 db referred to typical full scale -20 db -60 db thd+n - -105 -91 -51 -99 - -45 db double-speed mode fs = 96 khz dynamic range a-weighted unweighted 40 khz bandwidth unweighted 108 105 - 114 111 108 -db total harmonic distortion + noise -1 db referred to typical full scale -20 db -60 db 40 khz bandwidth -1db thd+n - -105 -91 -51 -102 -99 - -45 - db quad-speed mode fs = 192 khz dynamic range a-weighted unweighted 40 khz bandwidth unweighted 108 105 - 114 111 108 -db total harmonic distortion + noise -1 db referred to typical full scale -20 db -60 db 40 khz bandwidth -1db thd+n - -105 -91 -51 -102 -99 - -45 - db dynamic performance for all modes interchannel isolation - 110 - db dc accuracy interchannel gain mismatch - 0.1 - db gain error -5 - 5 % gain drift - 100 - ppm/c offset error hpf enabled hpf disabled 0 - - - - 100 lsb analog input characteristics full-scale differential input voltage 1.07*va 1.13*va 1.19*va vpp input impedance (differential) - 250 - k common mode rejection ratio cmrr - 82 - db
ds626f2 13 cs5366 analog performance (automotive) test conditions (unle ss otherwise specified). va = 5.25 to 4.75 v, vd = 5.25 to 3.14 v, vls = vlc = 5.25 to 1.71 v and t a = -40 to +85 c. full-scale input sine wave. measurement bandwidth is 10 hz to 20 khz. parameter symbol min typ max unit single-speed mode fs = 48 khz dynamic range a-weighted unweighted 106 103 114 111 -db total harmonic distortion + noise -1 db referred to typical full scale -20 db -60 db thd+n - -105 -91 -51 -97 - -45 db double-speed mode fs = 96 khz dynamic range a-weighted unweighted 40 khz bandwidth unweighted 106 103 - 114 111 108 -db total harmonic distortion + noise -1 db referred to typical full scale -20 db -60 db 40 khz bandwidth -1 db thd+n - -105 -91 -51 -102 -97 - -45 - db quad-speed mode fs = 192 khz dynamic range a-weighted unweighted 40 khz bandwidth unweighted 106 103 - 114 111 108 -db total harmonic distortion + noise -1 db referred to typical full scale -20 db -60 db 40 khz bandwidth -1 db thd+n - -105 -91 -51 -102 -97 - -45 - db dynamic performance for all modes interchannel isolation - 110 - db dc accuracy interchannel gain mismatch - 0.1 - db gain error -7 - 7 % gain drift - 100 - ppm/c offset error hpf enabled hpf disabled 0 - - - - 100 lsb analog input characteristics full-scale input voltage 1.02*va 1.13*va 1.24*va vpp input impedance (differential) 250 - k common mode rejection ratio cmrr - 82 - db
14 ds626f2 cs5366 digital filter characteristics notes: 1. the filter frequency response scales precisely with fs. 2. response shown is for fs equal to 48 kh z. filter characteristics scale with fs. overflow timeout logic "0" = gnd = 0 v; logic "1" = vls; c l = 30 pf, timing threshold is 50% of vls. parameter symbol min typ max unit single-speed mode (2 khz to 54 khz sample rates) passband (note 1) (-0.1 db) 0 - 0.47 fs passband ripple -0.035 0.035 db stopband (note 1) 0.58 - fs stopband attenuation -95 db total group delay (fs = output sample rate) t gd -12/fs s double-speed mode (54 khz to 108 khz sample rates) passband (note 1) (-0.1 db) 0 - 0.45 fs passband ripple -0.035 0.035 db stopband (note 1) 0.68 - fs stopband attenuation -92 db total group delay (fs = output sample rate) t gd -9/fs s quad-speed mode (108 khz to 216 khz sample rates) passband (note 1) (-0.1 db) 0 - 0.24 fs passband ripple -0.035 0.035 db stopband (note 1) 0.78 - fs stopband attenuation -92 db total group delay (fs = output sample rate) t gd -5/fs s high-pass filter characteristics frequency response (note 2) -3.0 db -0.13 db - 1 20 -hz phase deviation (note 2) @ 20 hz - 10 - deg passband ripple -0db filter settling time 10 5 /fs - s parameter symbol min typ max unit ovfl time-out on overrange condition fs = 44.1 khz fs = 192 khz - (2 17 -1)/fs 2972 683 -ms
ds626f2 15 cs5366 serial audio interface - i2s/lj timing the serial audio port is a three-pin inte rface consisting of sclk, lrck and sdout. logic "0" = gnd = 0 v; logic "1" = vls; c l = 20 pf, timing threshold is 50% of vls. notes: 1. duty cycle of generated sclk depends on duty cycle of received mclk as specified under ?system clocking? on page 10 . 2. clkmode functionality described in section 4.6.3 "master mode clock dividers" on page 24 . 3. in slave mode, the sclk/lrck ratio can be set a ccording to preference. however, chip performance is guaranteed only when using the ratios in section 4.7 master and slave clock frequencies on page 25 . figure 3. i2s/lj timing parameter symbol min typ max unit sample rates single-speed mode double-speed mode quad-speed mode - 2 54 108 - 54 108 216 khz master mode sclk frequency sclk period 1/(64*216 khz) sclk duty cycle (note 1) (clkmode = 0) (note 2) (clkmode = 1) (note 2) - t period t high t high 64*fs 72.3 40 28 - - 50 33 64*fs - 60 38 hz ns % % lrck setup before sclk rising lrck hold after sclk rising t setup1 t hold1 20 20 --ns sdout setup before sclk rising sdout hold after sclk rising (vls = 1.8 v) after sclk rising (vls = 3.3 v) after sclk rising (vls = 5 v) t setup2 t hold2 t hold2 t hold2 10 20 10 5 --ns slave mode sclk frequency (note 3) sclk period 1/(64*216 khz) sclk duty cycle - t period t high - 72.3 28 64*fs - - - - 65 hz ns % lrck setup before sclk rising lrck hold after sclk rising t setup1 t hold1 20 20 --ns sdout setup before sclk rising (vls = 1.8 v) before sclk rising (vls = 3.3 v) before sclk rising (vls = 5 v) sdout hold after sclk rising (vls = 1.8 v) after sclk rising (vls = 3.3 v) after sclk rising (vls = 5 v) t setup2 t setup2 t setup2 t hold2 t hold2 t hold2 4 10 10 20 10 5 --ns lrck sdout sclk data channel channel data t hold2 t setup2 t hold1 t setup1 t period t high
16 ds626f2 cs5366 serial audio interface - tdm timing the serial audio port is a three-pin inte rface consisting of sclk, lrck and sdout. logic "0" = gnd = 0 v; logic "1" = vls; c l = 20 pf, timing threshold is 50% of vls. notes: 1. tdm quad-speed mode only specified to operate correctly at vls 3.14 v. 2. duty cycle of generated sclk depends on duty cycle of received mclk as specified under ?system clocking? on page 10 . 3. clkmode functionality described in section 4.6.3 "master mode clock dividers" on page 24 . 4. in slave mode, the sclk/lrck ratio can be set acco rding to preference; chip performance is guaran- teed only when using the ratios in section 4.7 master and slave clock frequencies on page 25 . figure 4. tdm timing parameter symbol min typ max unit sample rates single-speed mode double-speed mode quad-speed mode 1 - - - 2 54 108 - - - 54 108 216 khz khz khz master mode sclk frequency sclk period 1/(256*216 khz) sclk duty cycle (note 2) (clkmode = 0) (note 3) (clkmode = 1) (note 3) t period t high1 t high1 256*fs 18 40 28 - - 50 33 256*fs - 60 38 hz ns % % fs setup before sclk rising (single-speed mode) fs setup before sclk rising (double-speed mode) fs setup before sclk rising (quad-speed mode) fs width in sclk cycles t setup1 t setup1 t setup1 t high2 20 18 5 128 - - - - - - - 128 ns ns ns - sdout setup before sclk rising sdout hold after sclk rising t setup2 t hold2 5 5 - - - - ns ns slave mode sclk frequency (note 4) sclk period 1/(256*216 khz) sclk duty cycle t period t high1 - 18 28 256*fs - - - - 65 hz ns % fs setup before sclk rising (single-speed mode) fs setup before sclk rising (double-speed mode) fs setup before sclk rising (quad-speed mode) fs width in sclk cycles t setup1 t setup1 t setup1 t high2 20 20 10 1 - - - - - - - 244 ns ns ns - sdout setup before sclk rising sdout hold after sclk rising t setup2 t hold2 5 5 - - - - ns ns fs sdout sclk data data t hold2 t setup2 t setup1 new frame data t period t high1 t high2
ds626f2 17 cs5366 switching specifications - control port - i2c timing inputs: logic 0 = dgnd, logic 1 = vlc, sda c l =30pf notes: 1. data must be held for sufficient ti me to bridge the transition time, t fc , of scl. figure 5. i2c timing parameter symbol min max unit scl clock frequency f scl - 100 khz rst rising edge to start t irs 600 - ns bus free time between transmissions t buf 4.7 s start condition hold time (prior to first clock pulse) t hdst 4.0 s clock low time t low 4.7 clock high time t high 4.0 setup time for repeated start condition t sust 4.7 sda hold time from scl falling (note 1) t hdd 0 sda setup time to scl rising t sud 600 ns rise time of scl and sda t rc -1s fall time scl and sda t fc -300ns setup time for stop condition t susp 4.7 - s acknowledge delay from scl falling t ack 300 1000 ns t buf t hdst t lo w t hdd t high t sud stop sta rt sda scl t irs rst t hdst t rc t fc t sust t susp start stop repe ated t rd t fd t ack
18 ds626f2 cs5366 switching specificat ions - control po rt - spi timing inputs: logic 0 = dgnd, logic 1 = vlc, cdout c l =30pf notes: 1. data must be held for sufficient time to bridge the transition time of cclk. 2. for f sck <1 mhz figure 6. spi timing parameter symbol min max units cclk clock frequency f sck 06.0mhz rst rising edge to cs falling t srs 20 - ns cs falling to cclk edge t css 20 cs high time between transmissions t csh 1.0 s cclk low time t scl 66 ns cclk high time t sch 66 cdin to cclk rising setup time t dsu 40 cclk rising to data hold time (note 1) t dh 15 cclk falling to cdout stable t pd - 50 rise time of cdout t r1 25 fall time of cdout t f1 rise time of cclk and cdin (note 2) t r2 100 fall time of cclk and cdin (note 2) t f2 cs cclk cdin cdout rst t srs t scl t sch t css t r2 t f2 t csh t dsu t dh t pd
ds626f2 19 cs5366 4. applications 4.1 power cs5366 features five independent power pins that po wer various functional blocks within the device and allow for convenient interfacing to other devices. table 1 shows what portion of the device is powered from each supply pin. please refer to ?recommended operating conditions? on page 10 for the valid range of each power supply pin. the power supplied to each power pin can be independent of the power supplied to any other pin. to meet full performance specifications, the cs 5366 requires normal low-noise board layout. the ?typical connection diagram? on page 9 shows the recommended power arrangements, with the va pins connected to a clean supply. vd, which powers the digital filter , may be run from the system logic supply, or it may be powered from the analog supply via a single-pole decoupling filter. decoupling capacitors should be placed as near to th e adc as possible, with t he lower value high-frequen- cy capacitors placed nearest to the device leads. clo cks should be kept away from the filt+ and vq pins in order to avoid unwanted coupling of these signals into the device. the filt+ and vq decoupling capac- itors must be positioned to minimize the electrical path to ground. the cdb5366 evaluation board demonstrat es optimum layout for the device. 4.2 control port mode a nd stand-alone operation 4.2.1 stand-alone mode in stand-alone mode, the cs5366 is programmed excl usively with multi-use configuration pins. this mode provides a set of commonly used features, which compri se a subset of the complete set of device features offered in cont rol port mode. to use the cs5366 in stand-alone mode, the configuration pins must be held in a stable state, at valid logic levels, and rst must be asserted until the power supplies and clocks are stable and valid. more informa- tion on the reset function is available in section 4.5 on page 22 . 4.2.2 control port mode in control port mode, all features of the cs5366 are available. four multi-use configuration pins become software pins that support the i2c or spi bus protocol. to initiate control port mode, a controller that sup- ports i2c or spi must be used to enable the internal register functionality. this is done by setting the cp- en bit (bit 7 of the global control port register). on ce cp-en is set, all of the device configuration pins are ignored, and the internal register settings determine the operating modes of the part. figure 4.13 on page 30 provides detailed information about the i2c and spi bus protocols. power supply pin pin name pin number functional block va 4, 9 analog core vx 20 crystal oscillator vd 33 digital core vls 28 serial audio interface vlc 35 control logic table 1. power supply pin definitions
20 ds626f2 cs5366 4.3 master clock source the cs5366 requires a master clock t hat can come from one of two sour ces: an on-chip crystal oscillator driver or an externally generated clock. 4.3.1 on-chip crystal oscillator driver when using the on-board crystal os cillator driver, the xti pin (pin 21 ) is the input fo r the master clock (mclk) to the device. the xto pin (p in 22) must not be used to driv e anything other than the oscillator tank circuitry. when using the on-board crystal driver, the topology shown in figure 7 must be used. the crystal oscillator manufacturer supp lies recommended capac itor values. a buffered copy of the xti input is available as an output on the mclk pin (pin 23), wh ich is level-controlled by vls and may be used to syn- chronize other parts to the device. figure 7. crystal oscillator topology 4.3.2 externally gene rated master clock if an external clock is used, the xti and xto pins mu st be grounded, and the mclk pin becomes an input for the system master clock. the incoming mclk should be at the logic level set by the user on the vls supply pin. xti xto 22 21
ds626f2 21 cs5366 4.4 master and slave operation cs5366 operation depends on two clocks that are syn chronously derived from mclk: sclk and lrck/fs. see section 4.5 on page 22 for a detailed description of sclk and lrck/fs. the cs5366 can operate as either clock master or cl ock slave with respect to sclk and lrck/fs. in mas- ter mode, the cs5366 derives sclk and lrck/fs sy nchronously from mclk and outputs the derived clocks on the sclk pin (pin 25) and the lrck/fs pin (p in 24), respectively. in slave mode, the sclk and lrck/fs are inputs, and the input signals must be syn chronously derived from mclk by a separate device such as another cs5366 or a microcontroller. figure 8 illustrates the clock flow of sclk and lrck/fs in both master and slave modes. the master/slave operation is controlled through the se ttings of m1 and m0 pins in stand-alone mode or by the m[1] and m[0] bits in the global mode control register in control port mode. see section 4.6 on page 23 for more information regarding the configuratio n of m1 and m0 pins or m[1] and m[0] bits. figure 8. mast er/slave clock flow 4.4.1 synchronization of multiple devices to ensure synchronous sampling in applications wher e multiple adcs are used, the mclk and lrck must be the same for all cs5366 devices in the system. if only one master clock source is needed, one solution is to place one cs5366 in master mode, and slave all of the other devi ces to the one master, as illustrated in figure 9 . if multiple master clock sources are needed, one solution is to supply all clocks from the same external source and time the cs5366 reset de-assertion with the falling edge of mclk. this will ensure that all converters begin sampling on the same clock edge. figure 9. master and slave clocki ng for a multi-channel application adc as clock master controller lrck/fs sclk adc as clock slave controller lrck/fs sclk master adc slave1 adc slave2 adc slave3 adc sclk & lrck/fs
22 ds626f2 cs5366 4.5 serial audio interface (sai) format the sai port consists of two timing pins (sclk, l rck/fs) and four audio data output pins (sdout1/tdm, sdout2, sdout3/tdm and sdout4). the cs5366 output is serial data in i2s, left-justified (lj), or time division multiplexed (tdm) digital au dio interface formats. these formats are available to the user in both stand-alone mode and control port mode. 4.5.1 i2s and lj format the i2s and lj formats are both two-channel protocols. during one lrck period, two channels of data are transmitted, odd channels first, then even. the msb is alwa ys clocked out first. in slave mode, the number of sclk cycles per channel is fixed as described under ?serial audio interface - i2s/lj timing? on page 15 . in slave mode, if more than 32 sclk cycles per channel are received from a master controller, the cs5 366 will fill the longer frame with trailing ze ros. if fewe r than 24 sclk cycles per channel are received from a master, the cs5366 will truncate the seri al data output to the number of sclk cycles received. for a complete overview of serial au dio interface formats, please refer to cirrus logic ap- plication note an282. figure 10. i2s format figure 11. lj format odd channels 1,3, ... even channels 2,4, ... lrck receiver latches data on rising edges of sclk sdout sclk msb ... lsb msb ... lsb msb odd channels 1,3, ... even channels 2,4, ... lrck receiver latches data on rising edges of sclk msb ... lsb msb msb ... lsb sdout sclk
ds626f2 23 cs5366 4.5.2 tdm format in tdm mode, all six channels of audio data are serially clocked out during a single frame sync (fs) cycle, as shown in figure 12 . the rising edge of fs signifies the star t of a new tdm frame cycle. each channel slot occupies 32 sclk cycles, with the data left ju stified and with msb first. tdm output data should be latched on the rising edge of sc lk within time specified under ?serial audio interface - tdm timing? section on page 16 . the tdm data output port resides on the sdout1 pin. the tdm output pin is complimentary tdm data. all sdout pins will remain active during tdm mode. refer to section 4.11 ?optimizing perfor- mance in tdm mode? on page 29 for critical system design information. figure 12. tdm format 4.5.3 configuring serial audio interface format the serial audio interface format of the data is controlle d by the configuration of the dif1 and dif0 pins in stand-alone mode or by the dif[1] an d dif[0] bits in the global mode control register in control port mode, as shown in table 2 . table 2. dif1 and dif0 pin settings 4.6 speed modes 4.6.1 sample rate ranges cs5366 supports sampling rates from 2 khz to 21 khz, divided into three ranges: 2 khz - 54 khz, 54 khz - 108 khz, and 108 khz - 216 khz. these sampling speed modes are called single-speed mode (ssm), double-speed mode (dsm), and quad-speed mode (qsm), respectively. 4.6.2 using m1 and m0 to set sampling parameters the master/slave operation and the sample rate rang e are controlled through the settings of the m1 and m0 pins in stand-alone mode, or by the m[1] and m[0] bits in the global mode control register in control port mode, as shown in table 3 . table 3. m1 and m0 settings dif1 dif0 mode 0 0 left-justified 01 i2s 10 tdm 11 reserved m1 m0 mode frequency range 0 0 single-speed master mode (ssm) 2 khz - 54 khz 0 1 double-speed master mode (dsm) 54 khz - 108 khz 1 0 quadruple-speed master mode (qsm) 108 khz - 216 khz 1 1 auto-detected speed slave mode 2 khz - 216 khz channel 6 sclk lsb msb lsb msb lsb msb lsb msb lsb msb lsb msb tdm out channel 1 channel 4 channel 2 channel 5 channel 3 32 clks 32 clks 32 clks 32 clks 32 clks 32 clks 32 clks 32 clks fs lsb lsb msb data zeroes
24 ds626f2 cs5366 4.6.3 master mode clock dividers figure 13 shows the configuration of the mc lk dividers and the sample rate dividers for master mode, in- cluding the significance of each mclk divider pin (i n stand-alone mode) or bit (in control port mode). figure 13. master mode clock dividers 4.6.4 slave mode audio cl ocking with auto-detect in slave mode, cs5366 auto-detects speed mode, which eliminates the need to configure m1 and m0 when changing among speed modes. the external mclk is su bject to clock dividers as set by the clock divider pins in stand-alone mode or the clock divider bits in control port mode. the cs5366 compares the divided- down, internal mclk to the incoming lrck/fs and sets the speed mode based on the mclk/lrck ratio as shown in figure 14 . figure 14. slave mode auto-detect speed 128 64 m0 m1 lrck/ fs single speed quad speed double speed 00 01 10 2 4 1 sclk single speed quad speed double speed 00 01 10 256 pin clkmode mdiv n/a mclk 1 1.5 2 1 2 1 bit mdiv1 mdiv0 0/1 0/1 0/1 mclk dividers sample rate dividers clkmode 128 64 single-speed 256 pin clkmode mdiv n/a external mclk 1 1.5 2 1 2 1 bit mdiv1 mdiv0 0/1 0/1 0/1 mclk dividers clkmode lrck lrck double-speed quad-speed speed mode internal mclk
ds626f2 25 cs5366 4.7 master and slave clock frequencies tables 4 through 12 show the clock speeds for sample rates of 48 khz, 96 khz and 192 khz. the mclk/lrck ratio should be kept at a co nstant value during each mode. in master mode, the device outputs the frequencies shown. in slave mo de, the sclk/lrck ratio can be set according to design preference. however, device performance is guaranteed only when using the ratios shown in the tables. table 4. frequencies for 48 khz sample rate using lj/i2s table 5. frequencies for 96 khz sample rate using lj/i2s table 6. frequencies for 192 khz sample rate using lj/i2s table 7. frequencies for 48 khz sample rate using tdm table 8. frequencies for 48 khz sample rate using tdm control port mode only lj/i2s master or slave ssm fs = 48 khz mclk divider 4 3 2 1.5 1 mclk (mhz) 49.152 36.864 24.576 18.384 12.288 sclk (mhz) 3.072 3.072 3.072 3.072 3.072 mclk/lrck ratio 1024 768 512 384 256 sclk/lrck ratio 64 64 64 64 64 lj/i2s master or slave dsm fs = 96 khz mclk divider 4 3 2 1.5 1 mclk (mhz) 49.152 36.864 24.567 18.384 12.288 sclk (mhz) 6.144 6.144 6.144 6.144 6.144 mclk/lrck ratio 512 384 256 192 128 sclk/lrck ratio 64 64 64 64 64 lj/i2s master or slave qsm fs = 192 khz mclk divider 4 3 2 1.5 1 mclk (mhz) 49.152 36.864 24 18.384 12.288 sclk (mhz) 12.288 12.288 12.288 12.288 12.288 mclk/lrck ratio 256 192 128 96 64 sclk/lrck ratio 64 64 64 64 64 tdm master ssm fs = 48 khz mclk divider 4 3 2 1.5 1 mclk (mhz) 49.152 36.864 24.567 18.384 12.288 sclk (mhz) 12.288 12.288 12.288 12.288 12.288 mclk/fs ratio 1024 768 512 384 256 sclk/fs ratio 256 256 256 256 256 tdm slave ssm fs = 48 khz mclk divider 4 3 2 1.5 1 mclk (mhz) 49.152 36.864 24.567 18.384 12.288 sclk (mhz) 12.288 12.288 12.288 12.288 12.288 mclk/fs ratio 1024 768 512 384 256 sclk/fs ratio 256 256 256 256 256
26 ds626f2 cs5366 table 9. frequencies for 96 khz sample rate using tdm table 10. frequencies for 96 khz sample rate using tdm table 11. frequencies for 192 khz sample rate using tdm table 12. frequencies for 192 khz sample rate using tdm tdm master dsm fs = 96 khz mclk divider 4 3 2- - mclk (mhz) 49.152 36.864 24.567 - - sclk (mhz) 24.576 24.576 24.576 - - mclk/fs ratio 512 384 256 - - sclk/fs ratio 256 256 256 - - tdm slave dsm fs = 96 khz mclk divider 4 3 2 1.5 1 mclk (mhz) 49.152 36.864 24.567 18.384 12.288 sclk (mhz) 24.576 24.576 24.576 24.576 24.576 mclk/fs ratio 512 384 256 192 128 sclk/fs ratio 256 256 256 256 256 tdm master qsm fs = 192 khz mclk divider 4 ---- mclk (mhz) 49.152 - - - - sclk (mhz) 49.152 - - - - mclk/fs ratio 256 - - - - sclk/fs ratio 256 - - - - tdm slave qsm fs = 192 khz mclk divider 4 3 2 1.5 1 mclk (mhz) 49.152 36.864 24.567 18.384 12.288 sclk (mhz) 49.152 49.152 49.152 49.152 49.152 mclk/fs ratio 256 192 128 96 64 sclk/fs ratio 256 256 256 256 256
ds626f2 27 cs5366 4.8 reset the device should be held in reset until power is applied and all incoming clocks are stable and valid. upon de-assertion of rst , the state of the configuratio n pins is latched, the state machine begins, and the device starts sending audio output data a maximum of 524288 mclk cycles after the release of rst . when chang- ing between mode configurations in stand-alone mode, including clock dividers, serial audio interface for- mat, master/slave, or speed modes, it is recommended to reset the device following the change by holding the rst pin low for a minimum of one mclk cycle and th en restoring the pin to a logic-high condition. 4.8.1 power-down mode the cs5366 features a power-down mode in which power is temporarily withheld from the modulators, the crystal oscillator driver, the digita l core, and the serial port. the us er can access power-down mode by holding the device in reset and holding all clock lines at a static, valid logic level (e ither logic-high or logic- low). ?dc power? on page 11 shows the power-saving associated with power-down mode. 4.9 overflow detection 4.9.1 overflow in stand-alone mode the cs5366 includes overflow detection on all input channels. in stand-alone mode, this information is presented as open drain, active low on the ovfl pin. the pin will go to a logical low as soon as an over- range condition in any channel is detected. the data will remain low, then time-out as specified in section "overflow timeout" on page 14 . after the time-out, the ovfl pin will return to a logical high if there has not been any other over-r ange condition detected. note that an over-range conditi on on any channel will restart the time-out period. 4.9.2 overflow in control port mode in control port mode, the overflow status register interacts with the overflow mask register to provide interrupt capability for each individual channel. see section 5.4 "02h (ovfl) ov erflow status register" on page 33 for details on these two registers.
28 ds626f2 cs5366 4.10 analog connections the analog modulator samples the input at half of th e internal master clock frequency, or 6.144 mhz nom- inally. the digital filter will reject signals within the stopband of the f ilter. however, there is no rejection of input signals that are at (n x 6.144 mhz) the di gital passband frequency, where n=0,1,2.... refer to figure 15 , which shows the suggested filter that will attenuate any noise ener gy at 6.144 mhz in addition to providing the optimum source impedance for the modula tors. the use of capacitor s that have a large volt- age coefficient (such as general-purpose ceramics) must be avoided since these can degrade signal linear- ity. cog capacitors are recommended for this applicat ion. for additional configurations, refer to cirrus application note an241. figure 15. recommended analog input buffer vq + 634 634 91 91 + - - 2700 pf 470 pf 470 pf cog cog 10 uf 10 uf adc ain+ adc ain- ain+ ain- cog 100 k 10 k 10 k 100 k
ds626f2 29 cs5366 4.11 optimizing performance in tdm mode noise management is a design techni que that is utilized in th e majority of audio a/ d converters. noise man- agement is relatively simple conceptually. the goal of noise management is to interleave the on-chip digital activity with the analog sampling processes to ensure th at the noise generated by th e digital activity is min- imized (ideally non-existant) wh en the analog sampling occurs. noise management, when implemented properly, minimizes the on-chip interference between the analog and digital sections of the device. this technique has proven to be very effective and has si mplified the process of implementing an a/d converter into a systems design. the dominate source of interference (and most difficult to control) is the activity on the serial audio interface (sai). however, noise manag ement becomes more difficult to implement as audio sample rates increase simp ly due to the fact that there is le ss time between transitions on the sai. the cs5366 a/d converter supports a multi-channel ti me-division-multiplexed in terface for single, double and quad-speed sampling modes. in single-speed mode, sample rates below 50 khz, the required fre- quencies of the audio serial ports are sufficiently low th at it is possible to im plement noise-management. in this mode, the performance of th e devices are relatively immune to activity on the audio ports. however, in double-speed and quad-speed modes there is insufficient time to implement noise manage- ment due to the required frequencies of the audio ports. therefore, analog performance, both dynamic range and thd+n, can be degraded if the serial por t transitions occurr concurrently with the analog sam- pling. the magnitude of the interference is not only relat ed to the timing of the tran sition but also the di/dt or transient currents associated with the ac tivity on the serial ports. even th ough there is insufficient time to properly implement noise management , the interfer ence effects can be minimized by controlling the tran- sient currents required of the serial ports in double- and quad-speed tdm modes. in addition to standard mixed-signal design techniqu es, system performance can be maximized by following several guidelines during design. ? operate the serial audio port at 3.3 v and not 5 v. the lower serial port voltage lowers transent currents. ? operate the a/d converter as a system clock slave. the serial clock and left /right clock become high- impedence inputs in this mode and do not generate significant transient currents. ? place a buffer on the serial data output very near the a/d converter. minimi zing the stray capacitance of the printed circuit boar d trace and the loading presented by ot her devices on the serial data line will minimize the transient current. ? place a resistor, near the converte r, beween the a/d serial data output and the buffer. this resistor will reduce the instantaneous switching currents into the capacitive loads on the nets, resulting in a slower edge rate. the value of the resistor should be as high as possible without causing timing problems elsewhere in the system. 4.12 dc offset control the cs5366 includes a dedicated high-pass filter for each channel to remove input dc offset at the system level. a dc level may result in audi ble ?clicks? when switching between devices in a multi-channel system. in stand-alone mode, all of the high-pass filters remain enabled. in control port mode, the high-pass filters default to enabled, but may be controlled by writing to the hpf register. if any hpf bit is taken low, the re- spective high-pass filter is enabled, and it continuously subt racts a measure of the dc offset from the output of the decimation filter. if any hpf bit is taken high during device operation, the value of the dc offset reg- ister is frozen, and this dc o ffset will continue to be subtracted from the conversion result.
30 ds626f2 cs5366 4.13 control port operation the control port is used to read and write the inter nal device registers. it s upports two industry standard formats, i2c and spi. the part is in i2c format by default. spi mode is selected if there is ever a high-to-low transition on the ad0/cs pin after the rst pin has been restored high. in control port mode, all features of the cs5366 ar e available. four multi-use configuration pins become software pins that support the i2c or spi bus protocol. to initiate control port mode, a controller that sup- ports i2c or spi must be used to enable the internal register functionality. this is done by setting the cp-en bit (bit 7 of the global control port register). once cp-en is set, all of the device configuration pins are ignored, and the internal register settings determine the operating modes of the part. 4.13.1 spi mode in spi mode, cs is the cs5366 chip select signal; ccl k is the control port bit cl ock (input into the cs5366 from a controller); cdin is the input data line from a co ntroller; cdout is the output data line to a controller. data is clocked in on the rising edge of cclk and is supplied on the falling edge of cclk. to write to a register, bring cs low. the first se ven bits on cdin form the chip address and must be 1001111. the eighth bit is a read/write indicator (r/w), which should be low to write. the next eight bits form the memory address pointer (map), which is set to the address of the register that is to be updated. the next eight bits are the data that will be placed into the register desig nated by the map. during writes, the cdout output stays in the hi- z state. it may be externally pulled high or low with a 47 k resistor, if desired. there is a map auto-increm ent capability, which is e nabled by the incr bit in the map register. if incr is a zero, the map will stay constant fo r successive read or wr ites. if incr is set to a 1, the map will auto- increment after each byte is read or written, allo wing block reads or writes of successive registers. to read a register, the map has to be set to the correct address by exec uting a partial write cycle that fin- ishes (cs high) immediately after the map byte. the map auto-increment bit (incr) may be set or not, as desired. to begin a read, bring cs low, send out the chip address and set the read/write bit (r/w ) high. the next falling edge of cclk will clock out the msb of the addressed register (cdout will leave the high impedance state). if the map auto-increment bit is set to 1, the data for successi ve registers will appear consecutively . figure 16. spi format map msb lsb data byte 1 byte n r/w r/w address chip address chip cdin cclk cs cdout msb lsb msb lsb 1001111 1001111 map = memory address pointer, 8 bits, msb first high impedance
ds626f2 31 cs5366 4.13.2 i2c mode in i2c mode, sda is a bidirectional da ta line. data is clocked into and out of the part by the clock, scl. there is no cs pin. pins ad0 and ad1 form the two least-significant bits of the chip address and should be connected through a resistor to vlc or dgnd, as desired. the state of the pins is latched when the cs5366 is being released from rst. a start condition is defined as a fallin g transition of sda while scl is high . a stop condition is a rising tran- sition of sda while scl is high. all other transitions of sda occur while scl is low. the first byte sent to the cs5366 after a start condition consists of a 7-bit chip address field and a r/w bit (high for a read, low for a write). the upper five bits of the 7-bit addre ss field are fixed at 10011. to communicate with a cs5366, the chip address field, which is the first byte sent to the cs5366, should match 10011 and be followed by the settings of the ad1 and ad0. the eighth bit of the address is the r/w bit. if the operation is a write, the next byte is the memory address pointer (map), which se lects the register to be r ead or written. if the op- eration is a read, the cont ents of the register pointed to by t he map will be output. setting the auto-incre- ment bit in map allows successive reads or writes of consecutive registers. each byte is separated by an acknowledge bit. the ack bit is output from the cs5366 after each input byte is read and is input to the cs5366 from the microcontroller after each transmitted byte. since the read operation cannot set the map, an aborte d write operation is used as a preamble. the write operation is aborted after the acknowledge for the m ap byte by sending a stop condition. the following pseudocode illustrates an ab orted write operat ion followed by a read operation. send start condition. send 10011xx0 (chip address & write operation). receive acknowledge bit. send map byte, auto increment off. receive acknowledge bit. send stop condition, aborting write. send start condition. send 10011xx1 (chip address & read operation). receive acknowledge bit. receive byte, contents of selected register. send acknowledge bit. send stop condition. figure 17. i2c write format figure 18. i2c read format 4 5 6 7 24 25 scl chip address (write) map byte data data +1 start ack stop ack ack ack 1 0 0 1 1 ad1 ad0 0 sda incr 6 5 4 3 2 1 0 7 6 1 0 7 6 1 0 7 6 1 0 0 1 2 3 8 9 12 16 17 18 19 10 11 13 14 15 27 28 26 data +n scl chip address (write) map byte data data +1 start ack stop ack ack ack 1 0 0 1 1 ad1 ad0 0 sda 1 0 0 1 1 ad1 ad0 1 chip address (read) start incr 6 5 4 3 2 1 0 7 0 7 0 7 0 no 16 8 9 12 13 14 15 4 5 6 7 0 1 20 21 22 23 24 26 27 28 2 3 10 11 17 18 19 25 ack data + n stop
32 ds626f2 cs5366 5. register map in control port mode, the bits in these registers are used to control all of th e programmable features of the adc. all registers above 0ah are reserved. 5.1 register quick reference 5.2 00h (revi) chip id code & revision register default: see description the chip id code & revision re gister is used to store the id and revision of the chip. bits[7:4] contain the chip id, where the cs5366 is represented with a value of 0x6. bits[3:0] contain the revision of the chip, where revision a is represented as 0x0, revision b is represented as 0x1, etc. 5.3 01h (gctl) global m ode control register default: 0x00 the global mode control register is used to control the master/slave speed modes, the serial audio data format and the master clock dividers for all channel s. it also contains a control port enable bit. bit[7] cp-en manages the control port mode. un til this bit is asserted, all pins behave as if in stand-alone mode. when this bit is asserted, all pins used in stand-alone mode are ignored, and the corresponding reg- ister values become functional. bit[6] clkmode setting this bit puts the part in 384x mode (divides xti by 1.5), and clearing the bit in- vokes 256x mode (divide xti by 1.0 - pass through). adr name76543210 00 revi chip-id[3 :0] revision[3:0] 01 gctl cp-en clkmode mdiv[1:0] dif[1:0] mode[1:0] 02 ovfl reserved reserved ovfl6 ovfl5 ovfl4 ovfl3 ovfl2 ovfl1 03 ovfm reserved reserved ovfm6 ovfm5 ovfm4 ovfm3 ovfm2 ovfm1 04 hpf reserved reserved hpf6 hpf5 hpf4 hpf3 hpf2 hpf1 05 reserved - - - - - - - - 06 pdne reserved pdn-bg pdn-osc reserved pdn65 pdn43 pdn21 07 reserved - - - - - - - - 08 mute reserved reserved mute6 mute5 mute4 mute3 mute2 mute1 09 reserved - - - - - - - - 0a sden reserved reserved sden3 sden2 sden1 r/w76543210 r chip-id[3:0] revision[3:0] r/w76543210 r/w cp-en clkmode mdiv[1: 0] dif[1:0] mode[1:0]
ds626f2 33 cs5366 bits[5:4] mdiv[1:0] each bit selects an xti divider. when either bit is low, an xti divide-by-1 function is selected. when either bit is high, an xti divide-by-2 fu nction is selected. with both bits high, xti is divid- ed by 4. the table below shows the composite xti division using both clkmode and mdiv[1:0]. bits[3:2] dif[1:0] determine which data format the serial au dio interface is usi ng to clock-out data. dif[1:0] 0x00 left-justified format 0x01 i2s format 0x02 tdm 0x03 reserved bits[1:0] mode[1:0] this bit field determines the device sample rate range and whether it is operating as an audio clocking master or slave. mode[1:0] 0x00 single-speed mode master 0x01 double-speed mode master 0x02 quad-speed mode master 0x03 slave mode all speeds 5.4 02h (ovfl ) overflow status register default: 0xff, no overflows have occurred. note: this register interacts with register 03h, the overflow mask register. the overflow status register is used to indicate an individual overflow in a channel. if an overflow condition on any channel is detected, the corresponding bit in this register is asserted (low) in addition to the open drain active low ovfl pin going low. each overflow status bit is sticky and is cleared only when read, pro- viding full interrupt capability. 5.5 03h (ovfm) over flow mask register default: 0xff, all overfl ow interrupts enabled. the overflow mask register is used to allow or prev ent individual channel overflow events from creating activity on the ovfl pin. when a particular bit is set low in the mask register, the corresponding overflow bit in the overflow status register is prevented from causing any activity on the ovfl pin. clkmode,mdiv[1],mdiv[0] description 000 divide-by-1 100 divide-by-1.5 001 or 010 divide-by-2 101 or 110 divide-by-3 011 divide-by-4 111 reserved r/w76543210 r reserved reserved ovfl6 ovfl5 ovfl4 ovfl3 ovfl2 ovfl1 r/w76543210 r/w reserved reserved ovfm6 ovfm5 ovfm4 ovfm3 ovfm2 ovfm1
34 ds626f2 cs5366 5.6 04h (hpf ) high-pass filt er register default: 0x00, all high-pass filters enabled. the high-pass filter register is used to enable or di sable a high-pass filter that exists for each channel. these filters are used to perform dc offset calibration, a procedure that is detailed in ?dc offset control? on page 29 . 5.7 05h reserved 5.8 06h (pdn) power down register default: 0x00 - everything powered up the power down register is used as needed to reduce the chip?s power consumption. bit[7] reserved bit[6] reserved bit[5] pdn-bg when set, this bit powers-down the bandgap reference. bit[4] pdn-osc controls power to the internal oscillator core . when asserted, the inte rnal oscillator core is shut down, and no clock is supplied to the chip. if the ch ip is running off an externally supplied clock at the mclk pin, it is also prevented from clocking the device internally. bit[ 2 :0] pdn when any bit is set, all clocks going to a channel pair are turned off, and the serial data outputs are forced to all zeroes. 5.9 07h reserved 5.10 08h (mute) mute control register default: 0x00, no channels are muted. the mute control register is used to mute or unmute the serial audio data output of individual channels. when a bit is set, that channel?s serial data is muted by forcing the output to all zeroes. r/w76543210 r/w reserved reserved hpf6 hpf5 hpf4 hpf3 hpf2 hpf1 r/w76543210 reserved - - - - - - - - r/w76543210 r/w reserved pdn-bg pdn-osc reserved pdn65 pdn43 pdn21 r/w76543210 reserved - - - - - - - - r/w76543210 r/w reserved reserved mute6 mute5 mute4 mute3 mute2 mute1
ds626f2 35 cs5366 5.11 09h reserved 5.12 0ah (sden ) sdout enable control register default: 0x00, all sdout pins enabled. the sdout enable control register is used to tri-stat e the serial audio data output pins. each bit, when set, tri-states the associated sdout pin. r/w76543210 reserved - - - - - - - - r/w76543210 r/w reserved reserved sden3 sden2 sden1
36 ds626f2 cs5366 6. filter plots figure 19. ssm passband figure 20. dsm passband figure 21. qsm passband 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0. 5 ?0.1 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 0.1 frequency (normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0. 5 ?0.1 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 0.1 frequency (normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.2 5 ?0.1 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 0.1 frequency (normalized to fs) amplitude (db)
ds626f2 37 cs5366 figure 22. ssm stopband figure 23. dsm stopband figure 24. qsm stopband 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 frequency (normalized to fs) amplitude (db) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 frequency (normalized to fs) amplitude (db) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 ?120 ?100 ?80 ?60 ?40 ?20 0 frequency (normalized to fs) amplitude (db)
38 ds626f2 cs5366 figure 25. ssm -1 db cutoff figure 26. dsm -1 db cutoff figure 27. qsm -1 db cutoff 0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0. 6 ?2 ?1.8 ?1.6 ?1.4 ?1.2 ?1 ?0.8 ?0.6 ?0.4 ?0.2 0 frequency (normalized to fs) amplitude (db) 0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0. 6 ?2 ?1.8 ?1.6 ?1.4 ?1.2 ?1 ?0.8 ?0.6 ?0.4 ?0.2 0 frequency (normalized to fs) amplitude (db) 0.2 0.22 0.24 0.26 0.28 0.3 0.32 0.34 0.36 0.38 0. 4 ?2 ?1.8 ?1.6 ?1.4 ?1.2 ?1 ?0.8 ?0.6 ?0.4 ?0.2 0 frequency (normalized to fs) amplitude (db)
ds626f2 39 cs5366 7. parameter definitions dynamic range the ratio of the rms value of the signal to the rms su m of all other spectral components over the specified bandwidth. dynamic range is a signal-to-noise ratio measurement over the spec ified bandwidth made with a -60 dbfs signal. 60 db is added to resulting measurement to refer the measurement to full scale. this technique ensures that the distortion components are below the noise level and do not affect the measure- ment. this measurement te chnique has been accepted by the audi o engineering society, aes17-199, and the electronic industries associat ion of japan, eiaj cp-307. express ed in decibels. the dynamic range is specified with and without an a-weighting filter. total harmonic distortion + noise the ratio of the rms value of the signal to the rms su m of all other spectral components over the specified bandwidth (typically 10 hz to 20 kh z), including distortion components. expressed in decibels. measured at -1 and -20 dbfs as suggested in aes17-1991 an nex a. specified using an a-weighting filter. frequency response a measure of the amplitude response variation from 10 hz to 20 khz relative to the amplitude response at 1 khz. units in decibels. interchannel isolation a measure of crosstalk between one channel and all re maining channels, measured for each channel at the converter's output with no signal to the input under te st and a full-scale signal applied to all other channels. units in decibels. interchannel gain mismatch the gain difference between left and right channels. units in decibels. gain error the deviation from the nominal full-scale an alog output for a full-scale digital input. gain drift the change in gain value with temperature. units in ppm/c. offset error the deviation of the mid-scale transition (111...111 to 000...000) from the ideal. units in mv. intrachannel phase deviation the deviation from linear phase within a given channel. interchannel phase deviation the difference in phase response between channels.
40 ds626f2 cs5366 8. package dimensions thermal characteristics inches millimeters dim min nom max min nom max a --- 0.055 0.063 --- 1.40 1.60 a1 0.002 0.004 0.006 0.05 0.10 0.15 b 0.007 0.009 0.011 0.17 0.22 0.27 d 0.343 0.354 0.366 8.70 9.0 bsc 9.30 d1 0.272 0.28 0.280 6.90 7.0 bsc 7.10 e 0.343 0.354 0.366 8.70 9.0 bsc 9.30 e1 0.272 0.28 0.280 6.90 7.0 bsc 7.10 e* 0.016 0.020 0.024 0.40 0.50 bsc 0.60 l 0.018 0.24 0.030 0.45 0.60 0.75 0.000 4 7.000 0.00 4 7.00 * nominal pin pitch is 0.50 mm controlling dimension is mm. jedec designation: ms026 parameter symbol min typ max unit allowable junction temperature - - 135 c package thermal resistance ja -48- c/w jc -15- e1 e d1 d 1 e l b a1 a 48l lqfp package drawing e1 e d1 d 1 e l b a1 a
ds626f2 41 cs5366 9. ordering information 10.revision history product description package pb-free grade temp range container order # cs5366 114db, 192khz, 6-channel a/d converter 48-pin lqfp yes commercial -40 to +85c tray cs5366-cqz tape & reel cs5366-cqzr automotive -40 to +105c tray cs5366-dqz tape & reel CS5366-DQZR cdb5366 evaluation board for cs5366 cdb5366 revision changes a1 initial release pp1 updated table under ?dc power? on page 11 . updated gain error specification under ?analog characteristics (commercial)? on page 12 added master mode specifications under ?serial audio interface - i2s/lj timing? on page 15 added master mode specifications under ?serial audio interface - tdm timing? on page 16 pp2 updated ?dc power? on page 11 . pp3 updated tdm timing specifications. see ?serial audio interface - tdm timing? on page 16. f1 final release added section 4.11 ?optimizing performance in tdm mode? on page 29 . f2 updated the wording of pin 24, lrck/fs, in the pin description table on page 7 to correctly reflect the high/low clocking state for odd-chan nel selection in i2s and lj modes. contacting cirrus logic support for all product questions and inquiries, c ontact a cirrus logic sales representative. to find the one nearest you, go to www.cirrus.com. important notice cirrus logic, inc. and its subsidiaries ("cirrus") believe that the information contained in this document is accurate and reli able. however, the information is subject to change without notice and is provided "as is" without warran ty of any kind (express or implied). customers are advised to ob tain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold s ubject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liabil ity. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for in fringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or impli ed under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights associated with the inf ormation contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. certain applications usin g semiconductor products may involve potential ri sks of death, personal injury, or severe prop- erty or environmental damage (? critical applications?). cirrus products are not designed, authorized or warranted for use in aircraft systems, military a pplications, products s urgically implanted into the body, automotive sa fety or security de- vices, life support products or other cri tical applications. inclus ion of cirrus products in s uch applications is under- stood to be fully at the customer?s risk and cirrus disclaims and makes no warranty, express, statutory or implied, including the implied warranties of merchantability and fitness for particular purpose, with regard to any cirrus product that is used in such a manner. if the customer or customer?s customer uses or permits the use of cirrus products in critical applications, customer agrees, by such use, to fully indemnify cirrus, its officers, directors, employees, distributors and other agents from any and all liability, including attorneys? fees and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners. i2c is a registered trademark of philips semiconductor. spi is a trademark of motorola, inc.

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